The present invention relates generally to integrated circuit (IC) features. More particularly, the present invention relates to a method and an apparatus for fabricating reduced contact holes, vias, and trench features in integrated circuits.
The semiconductor or integrated circuit (IC) industry aims to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures, such as, gate lengths in field-effect transistors and the width of conductive lines, is driven by lithographic performance.
Features, such as, contacts and vias, provide a conducting path for electrically connecting one device to another or for electrically connecting circuits on various layers of the chip. As the number of devices per unit area have increased, so has the number of contacts and vias necessary to route signals and power throughout the chip. This, in turn, has required a decrease in feature sizes, including contacts and vias, and in feature pitches.
Feature size has been steadily decreasing with the use of shorter lithographic or exposure wavelengths and resolution enhancement techniques, such as, phase shifting masks and off-axis illumination. However, even with such lithographic techniques, the feature size is usually constrained to a dimension approximately equal to the lithographic wavelength divided by two times the numerical aperture (NA) of the lens of the exposure system. For example, for 193 nanometer (nm) lithographic systems with NA=0.63, the minimum feature size is approximately 150 nm.
Thus, there is a need for a process of fabricating an integrated circuit having a feature size smaller than the lithographic wavelength associated therewith. There is a further need for a process of fabricating an integrated circuit having reduced dimensions of contacts, vias, lines, spaces, interconnects, gates, doped regions, and/or etched regions than is achievable using conventional lithographic systems. There is still a further need for a process of fabricating an integrated circuit having a reduced feature size that utilizes existing equipment and materials and does not significantly decrease throughout.
An exemplary embodiment relates to a method of fabricating reduced feature size in an integrated circuit. The integrated circuit includes a patterned photoresist layer provided over a substrate. The patterned photoresist layer being patterned with radiation at a lithographic wavelength and in accordance with a pattern on a mask or reticle. The method includes providing an electron beam to at least one area of an aperture included in the patterned photoresist layer. The aperture has sidewalls and a width. The method further includes transforming the sidewalls in response to the electron beam, and forming a feature in the substrate in accordance with the transformed sidewalls of the aperture.
Another exemplary embodiment relates to an integrated circuit fabrication system. The system includes a mask or reticle including an image of a feature. A photoresist layer provided over a semiconductor substrate including an aperture representative of the image of the feature, the aperture having a width and sidewalls. The system further includes a source of electromagnetic radiation configured to form a reduced width of the aperture by moving the sidewalls.
Still another exemplary embodiment relates to an integrated circuit fabrication process. The process includes reducing a width associated with a patterned area in a photoresist layer provided over a substrate. The patterned area is representative of a feature. The process further includes forming the feature in the substrate. The feature has the reduced width associated with the patterned area. The reducing step includes having an electron beam incident on at least a part of the patterned area.